Architecture

The entire critical path, in silicon

From the moment a packet hits the wire to the moment an order leaves it, every stage that matters runs inside the FPGA. There's no kernel in the way and no PCIe round-trip, so the timing holds steady down to the nanosecond.

CPU / HOST FPGA CARD EXCHANGE Customer OMS Trade & order management C / C++ integration API Trading / Ops GUI Risk & position reports, event triggers, config Market-data-only stream Normalized L2 feed to userspace PCIe DMA / FPGA REGISTERS UDP Offload ITCH Feed Handler & L2 Order Book (5–10 lvl) Business Logic · ACQ HLS (C/C++) or SystemVerilog strategy Pre-trade risk & Mass Quote Cancellation Order Processing OUCH order encode Hardware TCP/IP Stack Order egress MAC 10/40 GbE MAC 10/40 GbE Matching Engine UDP TCP · OUCH Deterministic wire-to-trade latency < 150 ns
Networking / lookup Strategy / risk Offload MAC (10/40 GbE) In-fabric data path
The pipeline

Five stages, no CPU in the loop

Each stage hands off to the next inside the same chip. The host sets things up and watches, but it never sits between the market and the matching engine.

01 · Ingress

UDP offload

Inbound market data is received and offloaded directly in fabric off the 10/40 GbE MAC, with no kernel network stack involved.

02 · Decode

ITCH & book build

The ITCH feed handler decodes messages and reconstructs a 5–10 level L2 order book entirely in hardware.

03 · Decide

ACQ + risk

The quoting engine and pre-trade risk evaluate the book in the same clock domain. MQC can pull every quote in sub-microsecond time.

04 · Encode

OUCH order processing

Triggered orders are encoded into the exchange's OUCH protocol directly in fabric, ready for egress.

05 · Egress

Hardware TCP/IP

A custom hardware TCP/IP stack sends the order out through the dedicated TCP MAC to the matching engine.

Result

< 150 ns wire-to-trade

The timing barely moves run to run, because the whole decision happens in the chip rather than in software.

Strategy integration

Run your own strategy

Nothing here is a black box. Generate cores from C/C++ with HLS, or bring your own SystemVerilog and run it virtualized in the fabric. Either way, you can replay captured traffic through it before it goes near production.

  • HLS path: compile C/C++ business logic into FPGA cores.
  • SystemVerilog path: deploy custom HDL strategy logic, virtualized to the device.
  • Deterministic backtest: replay captured PCAP/TCP through the same logic.
  • Two-machine harness: end-to-end, in-hardware replay validation.
Specifications
Wire-to-trade< 150 ns, deterministic (FPGA-dependent)
Market dataITCH UDP, in-fabric L2 book (5–10 levels)
Order entryOUCH over hardware TCP/IP
Networking10 GbE & 40 GbE, dedicated UDP & TCP MACs
RiskHardware MQC, sub-microsecond reaction
HardwareXilinx / AMD FPGA accelerator cards
ScaleMulti-symbol, multi-card, horizontal per rack

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