The platform

Everything from tick to trade, accelerated in hardware

Market access, quoting, risk, integration and validation in one stack. The parts that have to be fast run on the FPGA; your software handles strategy and configuration and stays out of the hot path.

Connectivity & market access

Direct exchange access, decoded in fabric

Market data and order entry travel dedicated hardware paths. An ITCH UDP feed handler reconstructs the order book in-fabric, while orders leave through an OUCH gateway over a custom hardware TCP/IP stack.

  • Market data ingress: ITCH UDP feed handler with in-fabric order book reconstruction.
  • Order entry: OUCH execution gateway over a custom hardware TCP/IP stack.
  • Networking: 10 GbE and 40 GbE, with dedicated UDP and TCP MACs.
  • Compatible with a wide range of Xilinx / AMD FPGA accelerator cards.
EXCHANGE Matching FPGA CARD UDP feed ITCH handler L2 order book 5–10 levels OUCH gateway TCP order entry
ACQ

Automatic Continuous Quotation

Book depth5–10 levels
Symbols / cardMultiple
Cards / serverMultiple
ScaleHorizontal, per rack
Trading engine

Quoting that lives inside the silicon

Automatic Continuous Quotation runs in fabric, driven by a configurable L2 order book. The same architecture scales from a single symbol to a full rack of FPGA cards.

  • In-fabric quoting driven by a configurable 5-to-10-level L2 book.
  • Multi-instrument, multi-FPGA scale: many symbols per card, many cards per server.
  • Market-data-only mode streams a low-latency normalized feed to userspace.
  • Full client strategy integration, including virtualized SystemVerilog logic deployed to the FPGA.
Pre-trade risk & MQC

Risk controls enforced in sub-microsecond hardware

Risk checks run in the fabric alongside everything else, so they keep pace with the market instead of trailing it. Mass Quote Cancellation reacts in fixed time, faster than any CPU-bound check could.

  • MQC on price band breach: fires when best bid/ask crosses a configured band.
  • MQC on trading halt: ACQ automatically resumes when the symbol re-opens.
  • Custom user-defined triggers driven by fills, order book state, and best bid/ask.
  • Deterministic, hardware-enforced, with low sub-microsecond reaction.
< 1 µs

Mass Quote Cancellation reaction

Integration, tooling & validation

Built for software teams

Your team works through interfaces it already knows: a C++ API to integrate against, a real-time GUI to operate, and a way to validate strategies in hardware before going live.

Integration & tooling

A C++ integration API and a trading/operations GUI provide:

  • Real-time event notifications and continuous position & risk reporting.
  • Exchange-specific message bypass for direct order entry.
  • Configuration of instruments, book depth, and event triggers.
  • Device-level provisioning of MAC and IPv4 addressing.

Backtesting & validation

Deterministic validation that exercises the same logic you deploy:

  • Deterministic backtest engine driving captured PCAP/TCP traffic.
  • Virtualized execution of custom SystemVerilog strategy logic.
  • Two-machine physical harness for end-to-end, in-hardware replay.
  • Validate behavior before a single order reaches production.

See the full architecture

Walk the complete wire-to-trade path through the FPGA, from UDP ingress to OUCH order entry.

View the technology → Talk to an engineer